Many semiconductor fabrication processes currently employ polycrystalline silicon (polysilicon) as a material for conductor interconnection purposes. This is due primarily to the ease with which polysilicon can be processed in semiconductor manufacturing, its low cost, as well as its ability to be highly doped to provide a low resistance conductor. In addition, the base or starting material of many semiconductor circuits comprises a single crystal silicon wafer with which the polysilicon is compatible for fabricating the circuits.
Typically, a doped polysilicon is deposited over a processed single crystal silicon semiconductor as a first step in forming a conductor for connecting one semiconductor region to another. The wafer is then masked and patterned to define the particular geometry of the conductor. An etch process, generally a plasma or dry etch, is employed to remove the undesired portions of the polysilicon material. One problem encountered in the polysilicon etching process is the inability to easily detect when the polysilicon has been removed down to its interface with the underlying single crystal silicon material. In fabricating certain integrated circuits, it is highly desirable to stop the etch process when the polysilicon material has been completely removed, such that the single crystal material is not exposed to the etch for a substantial period of time.
The foregoing desirability is particularly important in fabricating vertical bipolar transistor devices, in which the polysilicon material is patterned and etched to define an emitter opening therein. The etch extends down to the single crystal silicon material in which the active bipolar transistor regions are formed. The polysilicon material is preferably completely removed in the emitter opening so that impurities can be diffused or implanted into the single crystal silicon base region to thereby form an intrinsic transistor base region. However, a common problem with such a technique is that the polysilicon etching process cannot be controlled accurately enough to assure that the single crystal silicon base material is not exposed to the etching process.
A problem associated with the foregoing transistor fabrication technique, and considered to be severe, is that of silicon crystal damage due to the plasma etch. The plasma etch down to the single crystal base region often causes silicon crystal damage and surface roughening at the location where the emitter-base junction is to be formed. The damage to silicon as a result of reactive ion etching is well known, as discussed in the technical article entitled "Reactive Ion-etching-induced Damage In Silicon Using SF.sub.6 Gas Mixtures," J. Vac. Sci. Technol. B, Vol. 5, No. 4, Jul./Aug. 1987, pp. 876-882, and an article presented at the Fourth International Symposium on Semiconductor Processing, Jan. 1986, entitled "RIE Damage and its Control in Silicon Processing," pp. 163-172, by Fonash et al.
The etching of semiconductor circuit materials in general is often conducted by dry etch techniques employing plasma reactors. While plasma reactions are understood to a certain extent, a great deal of experimentation must yet be undertaken to develop suitable results when used in etch processes. This can be appreciated, as numerous different chemical and physical reactions take place in a plasma reaction. When considering the different chemical constituent elements employed in a plasma reaction, each of which react in many different ways to produce different results, the prediction as to the etching results are often unsatisfactory. The plasma etching of silicon semiconductor material has reached a stage such that a minimum knowledge and understanding has been gained in order to predict the results of the etching parameters for fabricating silicon circuits. Because silicon is the basic semiconductor material employed in fabricating semiconductor circuits, the focus on plasma etch developments has been directed to such material. Few, if any, development efforts have been undertaken in applying dry etch techniques to other semiconductor materials, such as germanium. This is due primarily to the fact that when germanium was widely utilized for fabricating semiconductor circuits and devices, plasma etching was unknown.
It is recognized today that the gases introduced into plasma reactors to provide the etching reactants readily react with silicon material and thereby etch polysilicon at essentially the same rate as that of the single crystal silicon material. Halogen gases are frequently utilized in plasma reactions to etch silicon. The halogen family of gases readily form volatile products with silicon, wherein the reaction by-products can be easily removed by exhausting the by-product gases.
While doping the polysilicon at impurity levels different than that of the single crystal material provides a certain degree of etch selectivity therebetween, even extreme doping level differences between the materials have not proven to provide a satisfactory etch rate difference. Current dry etch techniques have achieved at most an etch rate difference of 1:1.5 between silicon and polysilicon by utilizing different doping levels of the materials.
From the foregoing, it can be seen that a need exists for an improved dry etch technique which enables new semiconductor and non-homogeneous layers of materials in semiconductor circuits to be selectively etched. An additional need exists for a dry etch process which can quickly etch a material layer overlying the single crystal silicon material, but react with the underlying single crystal silicon material at a much lower rate, thereby reducing the exposure time of the base silicon material to the plasma process. There is yet another need for a dry etch chemistry which is adapted for etching a germanium interface layer more quickly than an underlying single crystal silicon base material.